Aeneon DDR2-1066MHz and DDR3-1333MHz 2GB KitsDDR2: CL5 and CL6 overclocking
Loosening further to CL5, here are our findings.
378MHz (756MHz DDR) was achieved with 5-3-3- timings. That's 28MHz (56MHz DDR) up from running 4-3-3-.
Loosening the sub-timings to -4-4- on CL5 gave us a big jump in speed. We got almost 150MHz (300MHz DDR) more than 5-3-3- with a clock of 512MHz (1024MHz DDR).
A maximum clock of 568MHz (1136MHz DDR) was achieved using 5-5-5- timings.
Let us have a go at CL6...
We were quite surprised that this pair actually runs CL6, but we didn't get any increase from running CL5.
The highest clock achieved on this pair of memory is found to be 1136MHz 5-5-5-15 at 2.0V. We tried going lower to 1.90V and it runs fine with the same settings.
378MHz (756MHz DDR) was achieved with 5-3-3- timings. That's 28MHz (56MHz DDR) up from running 4-3-3-.
Loosening the sub-timings to -4-4- on CL5 gave us a big jump in speed. We got almost 150MHz (300MHz DDR) more than 5-3-3- with a clock of 512MHz (1024MHz DDR).
A maximum clock of 568MHz (1136MHz DDR) was achieved using 5-5-5- timings.
Let us have a go at CL6...
We were quite surprised that this pair actually runs CL6, but we didn't get any increase from running CL5.
The highest clock achieved on this pair of memory is found to be 1136MHz 5-5-5-15 at 2.0V. We tried going lower to 1.90V and it runs fine with the same settings.
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